山东大学电子设计自动化(EDA)硬件实验-实验5 8位二进制数加法器

一:实验要求:

用两个4位二进制数加法器实现层次化设计：元件例化，即在顶层调用。
 用数码管显示(0,1,…9,A,b,C,d,E,F)

二:  实验仪器与器材

1.EDA 开发软件

2.微机

3.实验开发系统

4.打印机

5.其他器件与材料

三:实验内容

1. 源文件.

add_8如下:

LIBRARY IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity add_8 IS
 port (A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       CIN: IN STD_LOGIC;
       SUM:out std_logic_vector(7 downto 0);
       COUT: OUT STD_LOGIC);
end add_8;

ARCHITECTURE info OF add_8 IS
COMPONENT add_4
port(a,b:in std_logic_vector(3 downto 0);
     cin:in std_logic;
	  cout:out std_logic;
	  sum:out std_logic_vector(3 downto 0));
END COMPONENT;
signal SC:std_logic;
begin
U1:add_4
port map(cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),cout=>sc,sum=>sum(3 downto 0));
U2:add_4
port map(cin=>sc,a=>a(7 downto 4),b=>b(7 downto 4),cout=>cout,sum=>sum(7 downto 4));
END ARCHITECTURE info;

add_4:U1如下:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity add_4 is
port(a,b:in std_logic_vector(3 downto 0);
     cin:in std_logic;
	  cout:out std_logic;
	  sum:out std_logic_vector(3 downto 0));
end entity add_4;

architecture info of add_4 is
signal data:std_logic_vector(4 downto 0);
	begin
	data<=('0'& a)+('0' & b)+("0000" & cin);
	cout<=data(4);
	sum<=data(3 downto 0);
end info;

add_4:U2如下:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity add_4 is
port(a,b:in std_logic_vector(3 downto 0);
     cin:in std_logic;
	  cout:out std_logic;
	  sum:out std_logic_vector(3 downto 0));
end entity add_4;

architecture info of add_4 is
signal data:std_logic_vector(4 downto 0);
	begin
	data<=('0'& a)+('0' & b)+("0000" & cin);
	cout<=data(4);
	sum<=data(3 downto 0);
end info;

2.编译情况

3.引脚配置

4.仿真波形图